Memory
2x32KB L1 data and instruction cache, 512KB/256KB L2 cache integrated in MPC8548/MPC8543
Up to 2GB SDRAM system memory
Soldered
DDR2 with or without ECC
Up to 300 MHz memory bus frequency, depending on CPU
Up to 16GB soldered Flash disk (SSD solid state disk)
Up to 32MB additional DDR2 SDRAM, FPGA-controlled, e.g. for video data
16MB boot Flash
2MB non-volatile SRAM
With GoldCap backup
128KB non-volatile FRAM
Serial EEPROM 4kbits for factory settings
Mass Storage
Parallel IDE (PATA)
Up to 16GB soldered ATA Flash disk (SSD solid state disk)
Serial ATA (SATA)
Up to two ports via rear I/O J2
Transfer rates up to 150MB/s (1.5 Gbits/s)
Via PCI-to-SATA bridge
See interface configuration matrix showing possible I/O combinations (PDF)
I/O
USB (host)
Four USB 2.0 host ports
Via rear I/O J2
OHCI and EHCI implementation
Data rates up to 480Mbits/s
USB (client)
One USB client port on series A connector at front panel
Via UART-to-USB converter
For first operation and service
Data rates up to 115.2kbits/s
16-byte transmit/receive buffer
Handshake lines: none
Ethernet
Up to three 10/100/1000Base-T Ethernet channels with MPC8548/E (two channels with MPC8543/E)
Via rear I/O J2
See interface configuration matrix showing possible I/O combinations (PDF)
User-defined I/O
FPGA-controlled
Up to 64 I/O lines
Connection via rear I/O J2
Standard version provides 4 UARTs and 16 GPIO lines
See interface configuration matrix showing possible I/O combinations (PDF)
Rear I/O
Four USB 2.0
Up to three 1000Base-T Ethernet
Up to two SATA
Up to 64 I/O lines, FPGA-controlled
Reduces Ethernet/SATA interfaces
See interface configuration matrix showing possible I/O combinations (PDF)
FPGA
Standard factory FPGA configuration:
Main bus interface
16Z043_SDRAM - Additional SDRAM controller (32 MB)
16Z034_GPIO - GPIO controller (rear I/O 14 lines, 2 IP cores)
16Z125_UART - UART controller (controls rear I/O COM1..4)
The FPGA offers the possibility to add customized I/O functionality. See FPGA.
Miscellaneous
Real-time clock with GoldCap backup
Temperature sensor, power supervision and watchdog
CompactPCI® Bus
Compliance with CompactPCI® Core Specification PICMG 2.0 R3.0
System slot
32-bit/32-MHz PCIe®-to-PCI bridge
V(I/O): +3.3V (+5V tolerant)
Busless Operation
Board can be supplied with +5V, +3.3V and +12V from backplane, all other voltages are generated on the board
Backplane J1 connector used only for power supply
Electrical Specifications
Supply voltage/power consumption:
+5V (-3%/+5%), 800mA approx.
+3.3V (-3%/+5%), 350mA approx.
±12V (-5%/+5%), 1A approx.
Mechanical Specifications
Dimensions:
CompactPCI® 3U board embedded in MEN-standard 3U-CCA frame
For use with MEN's conduction cooled subrack, 0701-0054
Front panel: 9HP with cut-out for USB
Weight: 620g
Environmental Specifications
Temperature range (operation):
-40..+85°C Tcase (CCA frame) (screened)
0..+60°C Tcase (CCA frame) (screened, with 16 GB SSD Flash disk)
Convection cooled variety F50P also available
Temperature range (storage): -40..+85°C
Relative humidity (operation): max. 95% non-condensing
Relative humidity (storage): max. 95% non-condensing
Altitude: -300m to + 3,000m
Shock: 15g/11ms
Bump: 10g/16ms
Vibration (sinusoidal): 1g/10..150Hz
Conformal coating on request
MTBF
150,290h @ 40°C according to IEC/TR 62380 (RDF 2000)
Safety
PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers
EMC
Tested according to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and IEC1000-4-4 (burst)
BIOS
MENMON™
Software Support
Linux
VxWorks®
QNX® (on request; support of the FPU is currently not provided by QNX®)
INTEGRITY® (Green Hills® Software) support available. Please contact Green Hills® for further information.
OS-9® (on request)
For more information on supported operating system versions and drivers see Software.
