P507 - Quad RS422/485 Interface PMC

Software-configurable

Data rates up to 921,600 bit/s

60-byte transmit/receive buffer

Full-duplex operation with RS422, half-duplex operation with RS485

Isolation between channels: 500V

Compatible with 16550 UART

Memory

32MB SDRAM memory
• Soldered
• DDR2
• 132MHz memory bus frequency
• FPGA-controlled

2MB non-volatile Flash
• For FPGA data and Nios® firmware
• FPGA-controlled

FPGA

Standard factory FPGA configuration:
• Main bus interface
• Interrupt controller, SMBus controller
• 16Z125_UART - UART Controller
• 16Z043_SDRAM - SDRAM controller
• 16Z045_FLASH - Flash interface
• 16Z034_GPIO - GPIO controller

The FPGA offers the possibility to add customized I/O functionality. See FPGA.

PMC Characteristics (PCI)

Compliant with PCI Specification 2.2

32-bit/33-MHz, 3.3V V(I/O)

Target

Peripheral Connections

Via front panel on a shielded 50-pin HP D-Sub SCSI 2 receptacle connector

Electrical Specifications

Isolation voltage:
• 500 VAC

Supply voltage/power consumption:
• +5V (-3%/+5%), 120mA
• +3.3V (-5%/+5%), 9mA

Mechanical Specifications

Dimensions: conforming to IEEE 1386.1

Weight: 78g

Environmental Specifications

Temperature range (operation):
• -40..+85°C (qualified components)
• Airflow: min. 1.0m/s

Temperature range (storage): -40..+85°C

Relative humidity (operation): max. 95% non-condensing

Relative humidity (storage): max. 95% non-condensing

Altitude: -300m to + 3,000m

Shock: 15g/11ms

Bump: 10g/16ms

Vibration (sinusoidal): 1g/10..150Hz

Conformal coating on request

MTBF

1 152 181 h @ 40°C according to IEC/TR 62380 (RDF 2000)

Safety

PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

EMC

Conforming to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and IEC1000-4-4 (burst)

Software Support

Windows®

Linux

For more information on supported operating system versions and drivers see Downloads.

Flexible Configuration

Customized I/O functions can be added to the FPGA.

It depends on the board type, pin counts and number of logic elements which IP cores make sense and/or can be implemented. Please contact MEN for information on feasibility.

You can find more information on our web page "User I/O in FPGA"

FPGA Capabilities

FPGA Altera® Cyclone® II EP2C35
• 33,216 logic elements
• 483,840 total RAM bits
• Supports Nios® II soft processor

Connection
• Functions can be linked to Wishbone or Avalon® bus
• Available pin count: 46 pins (FPGA to USM™)
• Functions available via USM™ at front I/O connector

MEN offers a USM™ development kit and an FPGA Development Package as well as Flash update tools for different operating systems.

Rear I/O

Via Pn4 rear I/O connector

Cooling

Conduction Cooling

Please note that some of these options may only be available for large volumes. Please ask our sales staff for more information.

Article No.	Description	More
Linux
This product is designed to work under Linux. See below for potentially available separate software packages from MEN.
13Z017-06	MDIS5™ low-level driver sources (MEN) for 16Z034_GPIO and 16Z037_GPIO Requires an MDIS4™/2004 or MDIS5™ system package	Download Details
13Z025-90	Linux native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART	Download Details
Windows
This product is designed to work under Windows®. See below for potentially available separate software packages from MEN.
10Y000-78	Windows® Embedded Standard 7 BSP for F11S, F19P, F21P, G20, XM1L, XM2, MM1, MM2, SC21, SC24, BC50M, F206, F210, F215, F216, G215, P506, P507 and P511	Download Details
13P507-77	Windows® Installset (MEN) for P507 Includes all free drivers developed by MEN for the supported hardware.	Download w/o System Package Download with System Package Details

For operating systems not mentioned here contact MEN sales.