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Tailored I/O functions realized as IP cores for configuration in onboard FPGAs The 16Z029_CAN is a CAN controller FPGA IP core with CANopen support.
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16Z029_CAN - CAN Controller IP Core

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Diagram
16Z029_CAN Diagram

Larger picture of 16Z029_CAN Diagram

Main Features
  • FPGA IP Core
  • CAN Protocol Version 2.0A/B
  • - Standard and extended data frames
  • - 0..8 bytes data length
  • - Programmable bit rate up to 1 Mbps
  • Support of Remote Frames
  • 5 receive buffers (FIFO scheme)
  • 3 transmit buffers with prioritization
  • Maskable identifier filter
  • Programmable loop-back mode for self-test operation
  • Signaling and interrupt capabilities for receiver and transmitter error states
  • Wishbone bus interface
Description Open

This core provides CAN controller function based on the Motorola Scalable CAN (MSCAN Block Guide V02.14) Module and the Bosch CAN Protocol Standard Version 2.0 Part A and B.  Full CAN function - except power down, sleep, wake up mode and 16-/8-bit acceptance filtering - is provided. The Wishbone bus is used as the CPU interface.

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Technical Data

Size

Logic elements (Altera® Cyclone® device family): 2000 typ.

Pin count: 2

RAM: 1 x 4096 bits

System-Bus Interface

Wishbone bus interface compliant with Wishbone Specification B.3

32-bit data transfer, 33MHz bus frequency

Supported Wishbone bus cycles
• Single read/write
• Block read/write

CAN Functionality

One CAN channel

CAN Protocol Version 2.0A/B
• Standard and extended data frames
• 0..8 bytes data length
• Programmable data rate up to 1 Mbit/s

Support for remote frames

5 receive buffers (FIFO-scheme)

3 transmit buffer with prioritization

Maskable identifier filter

Programmable loop-back mode for self-test operation

Signaling and interrupt capabilities for receiver and transmitter error states

Software Open
Documentation Open
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