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Rugged Computer Boards and Systems for
Harsh, Mobile and Mission-Critical Environments
Harsh, Mobile and Mission-Critical Environments
16Z043_SDRAM - SDRAM Controller IP Core
Overview
Diagram
Main Features
- FPGA IP Core
- Supports up to 133 MHz clock frequency
- Single and burst transactions
- Wishbone bus interface
Description
This product is an SDRAM controller for FPGA to SDRAM interfaces. The main functionality is to connect the Wishbone bus to SDRAM memory, with up to 133 MHz clock frequency. Single and burst transactions are supported. The 16Z043-00 version of this IP core is for SDR (Single Data Rate) SDRAM while the 16Z043-01 is for DDR2 (Double Data Rate 2) SDRAM.
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Technical Data
Size
Logic elements (Altera® Cyclone® device family): 1200 (16Z043-00) or ~1100 (16Z043-01)
Pin count min: 38 for 16Z043-00, 43 for 16Z043-01
Pin count max: 57 for 16Z043-00, 43 for 16Z043-01
RAM: 5 x M4K (Cyclone® I and II) or 5 x M9K (Cyclone® III)
(3 x M4K and 3 x M9K for later revisions of 16Z043-00)
System-Bus Interface
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, up to 133MHz bus frequency
Supported Wishbone bus cycles
•
Single read/write
•
Burst read/write
Second Wishbone interface for enhanced data throughput
Flexible FIFO depth for best system integration
SDRAM Functionality
SDR SDRAM data width 16 or 32 bits (16Z043-00)
DDR2 SDRAM data width 16 bits (16Z043-01)
Variable CAS latency
Up to 133 MHz clock rate
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