16Z024_SRAM - SRAM Controller IP Core

The 16z024 shares entity ports with the IDE Controller 16z023 when both IDE and SRAM controllers are used in the FPGA.

This core is also available as a more flexible variant for the access of a memory device with asynchronous interface (e.g. SRAM or Flash ROM) which includes DP RAMs using a busy signal (low active) to signal an address match. The 16z024-02 is more flexible in that there is no size limitation to 4 MB and variable data widths (8-/16-/32-bit) and various memory configurations are supported.

MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.

By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.