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P598 - Conduction-Cooled FPGA-based USM™ Main PMC

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P598 - Conduction-Cooled FPGA-based USM Main PMC

Diagram

Main Features

Main PMC for USM™ Universal Submodules
Conduction-cooled (CCPMC)
1 USM™ slot
1 FPGA 33,216 LE (for user-defined I/O and Nios® soft core)
32 MB DDR2 SDRAM
2 MB Flash
-40 to +85°C with qualified components

Description Open

USM™ Universal Submodules make PMC modules more flexible than ever. The conduction-cooled main PMC P598 gets its specific function through the IP cores implemented inside the onboard FPGA. This function can be changed at any time through implementation of different IP cores. The corresponding line drivers are realized on the USM™ which is simply plugged on the P598.

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Technical Data Open

Functionality

User-defined through FPGA

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Line drivers and/or additional hardware implemented on USM™ Universal Submodule (not included)

Memory

32MB SDRAM memory
• Soldered
• DDR2
• 132MHz memory bus frequency
• FPGA-controlled

2MB non-volatile Flash
• For FPGA data and Nios® firmware
• FPGA-controlled

FPGA

Standard factory FPGA configuration:
• Main bus interface
• Altera® SOPC Unit incl. Nios® II/f soft processor, GPIO, UART and DDR2 SDRAM control
• Wishbone-to-Avalon®/Avalon®-to-Wishbone bridges
• Chameleon Table V2
• Interrupt controller, SMBus controller
• PCI to Wishbone bridge, ID EEPROM emulation
• 16Z045_FLASH - Flash interface
• 16Z034_GPIO - GPIO controllers (2 IP cores, for onboard LEDs and 8-bit I/O)

The FPGA offers the possibility to add customized I/O functionality. See FPGA.

USM™ Slot

One slot for a standard USM™ module

For implementation of line drivers and/or additional hardware

Miscellaneous

Eight onboard LEDs, FPGA-controlled

I²C interface to detect the USM™ module

PMC Characteristics (PCI)

Compliant with PCI Specification 2.2

32-bit/33-MHz, 3.3V V(I/O)

Target

Peripheral Connections

Via Pn4 rear I/O connector

Electrical Specifications

Isolation voltage:
• Voltage depends on implementation and signal routing of USM™

Supply voltage/power consumption:
• +5V (-3%/+5%), FPGA idle / US0 plugged: approx. 118mA, memory test / US0 plugged: 122mA
• +3.3V (-5%/+5%), FPGA idle / US0 plugged: 76mA, memory test / US0 plugged: 82mA

MTBF: 848,597h @ 40°C according to IEC/TR 62380 (RDF 2000)

Mechanical Specifications

Dimensions: conforming to IEEE 1386.1

In accordance with VITA 20 (proposed Draft Standard for Conduction Cooled PMC)

Weight: 36g (w/o USM™ module)

Environmental Specifications

Temperature range (operation):
• -40..+85°C (qualified components), conduction-cooled
• Airflow: min. 10m³/h

Temperature range (storage): -40..+85°C

Relative humidity (operation): max. 95% non-condensing

Relative humidity (storage): max. 95% non-condensing

Altitude: -300m to + 3,000m

Shock: 15g/11ms

Bump: 10g/16ms

Vibration (sinusoidal): 2g/10..150Hz

Conformal coating on request

Safety

PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

EMC

Radio disturbance: no connection outside housing, therefore radio disturbance not relevant

ESD/burst: no external interface connector, therefore ESD and burst not relevant

Software Support

Flash update tools for Windows®, Linux, VxWorks®

Driver software depending on implemented FPGA functions

For more information on supported operating system versions and drivers see Software.

FPGA

This product offers the possibility to add customized I/O functionality in FPGA.

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Flexible Configuration

Customized I/O functions can be added to the FPGA.

It depends on the board type, pin counts and number of logic elements which IP cores make sense and/or can be implemented. Please contact MEN for information on feasibility.

You can find more information on our web page "User I/O in FPGA"

FPGA Capabilities

FPGA Altera® Cyclone® II EP2C35
• 33,216 logic elements
• 483,840 total RAM bits
• Supports Nios® II soft processor

Connection
• Functions can be linked to Wishbone or Avalon® bus
• Available pin count: 46 pins (FPGA to USM™)
• Functions available via USM™ at rear I/O connector

MEN offers an FPGA Development Package as well as Flash update tools for different operating systems.
• Package comes with function-identical convection-cooled PMC module with front I/O
• Only for development of FPGA, independent of conduction cooling

MEN IP Cores

MEN offers a large number of standard IP cores.

Examples:
• IDE (e.g. PIO mode 0, UDMA mode 5)
• UARTs
• CAN bus
• Display control
• Fast Ethernet (10/100Base-T)
• ...

For IP cores developed by MEN please refer to our IP core overview.
• IP Core compare chart (PDF)

MEN also offers development of new (customized) IP cores.

Third-Party IP Cores

Third-party IP cores can also be used in combination with MEN IP cores.

Examples:
• www.altera.com
• www.opencores.org

FPGA Design Environment

Altera® offers free download of Quartus® II Web Edition
• Complete environment for FPGA and CPLD design
• Includes schematic- and text-based design entry
• Integrated VHDL and Verilog HDL synthesis and support for third-party synthesis software
• SOPC Builder system generation software
• Place-and-route, verification, and programming

Altera® Quartus® II Web Edition FPGA design tool

Standard P598 Models

Article No.	Description	More
15P598-00	USM™ main PMC, conduction cooled, -40..+85°C with qualified components	Photo

Miscellaneous Accessories

Article No.	Description
08US00-00	Universal Submodule for prototyping, -40..+85°C qualified

Software

Documentation Open

Article No.	Description	More
FPGA
16P599-00	Nios® PMC USM™ FPGA Development Package (MEN) (without Altera® Quartus® II) (license included in PMC USM™ FPGA Development Kit)	Download Details
OS independent
To use MDIS™ low-level drivers, you also need one of the MDIS4™ or MDIS5™ system packages available for Linux, VxWorks®, QNX® or OS-9® (MDIS™ = MEN Driver Interface System).
13Z017-06	MDIS5™ low-level driver sources (MEN) for 16Z034_GPIO and 16Z037_GPIO Requires an MDIS4™/2004 or MDIS5™ system package	Download Details
Linux
This product is designed to work under Linux. See below for potentially available separate software packages from MEN.
13Z100-91	Linux FPGA update tool (MEN)	Download Details
Windows
This product is designed to work under Windows®. See below for potentially available separate software packages from MEN.
13P599-77	Windows® Installset (MEN) for P599, P598 and PMC USM™ FPGA development kit Includes all free drivers developed by MEN for the supported hardware.	Download w/o System Package Download with System Package Details
13Z100-70	Windows® FPGA update tool (MEN)	Download Details
VxWorks
This product is designed to work under VxWorks®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z100-60	VxWorks® FPGA update tool (MEN)	Download Details
QNX
This product is designed to work under QNX®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z100-40	QNX® FPGA update tool (MEN)	Download Details

Article No.	Description	More
15P598-DS	P598 Data Sheet (PDF)	Download
20P598-00	P598 User Manual (PDF)	Download
20US00-00	USM™ Specification (PDF)	Download
21M199-00	P599/M199 Programmer's Guide (PDF)	Download