16Z055_HDLC - Single-Channel HDLC Controller IP Core

default memory size of the transfer buffer is 2 kB. One transfer buffer contains always only one frame. The baudrate can be set in ranges from 9600 bit/s up to 1 Mbit/s.

MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.

By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.