
Features
The PMC USM™ FPGA Development Package can be used with the P599 USM™ main PMC. It includes a sample design integrating the standard Wishbone and the Altera® Avalon® bus.
The user can add IP cores to the Wishbone bus by using MEN's Wishbone Bus Maker tool, which is part of the package and which can be used to generate the Wishbone bus. The Wishbone Bus Maker can generate multi-master and multi-slave bus systems.
A Wishbone-to-Avalon®-bridge and vice versa, an Avalon®-to-Wishbone-bridge - both developed by MEN - allow the additional integration of Avalon®-based IP cores and especially of the Nios® soft core from Altera®. Nios® connects to the Avalon® bus, where a UART module and a GPIO module for user LED control is already implemented as well. The user can now also add IP cores to the Avalon® bus by using the SOPC Builder tool from Altera®. The SOPC builder is a part of the Quartus® II development package of Altera® - see www.altera.com. It is not part of MEN's PMC USM™ FPGA Development Package.
Supported Operating System
Windows® XP/2000
Content
FPGA file
Quartus® archive
MEN BusMaker
Bootstrapper and Perl script
Not Included
Altera® Quartus® II
Documentation
Programmer's guide available as a separate download (PDF)
Notes
Please refer to the User Manual of the PMC USM™ FPGA Development Kit for a detailed description of the hardware related to this software package.
xRevision History
===== [ History of fileset 16P599-00 ] =====
-----[ 1.9 ]-----
[ 2007-08-20 09:16:07 by MBrenner ]
P599-00IC001B5.qar
Updated because of 16Z084_IDEPROM bugfix
Updated chameleon table
-----[ 1.8 ]-----
[ 2007-06-25 15:53:16 by MBrenner ]
P599-00IC001B4a.qar
Added Archive Files
P599-00IC001B4.qarlog was the first Archive available as download file
P599-00IC001B4a.qarlog is the updated Archive which is using the same fpga binary
-----[ 1.7 ]-----
[ 2007-06-25 10:48:10 by MBrenner ]
Add VHDL File to Archive
-----[ 1.6 ]-----
[ 2007-06-01 08:16:43 by MBrenner ]
First version released
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