M-Module™ USM™ FPGA Development Kit

Six SA-Adapter™ slots
• For direct onboard connection
• 46 I/O signals from/to SCSI 2 connector
• RS232 SA-Adapter™ SA1 included

Three 20-pin I/O connectors
• 46 I/O signals from/to SCSI 2 connector

Eight user LEDs at front, driven by I/O signals

M-Module™ M199 (USM™ main module)

CPU
• Nios® II soft processor
• 66MHz

Memory
• 32MB DDR2 SDRAM, soldered
• 8MB non-volatile Flash, for FPGA data and Nios® firmware

I/O at front panel (SCSI 2 connector)
• One LVTTL UART (for RS232 on AD99 via SA1 SA-Adapter™)

Functions in FPGA
• Main bus interface
• Altera® SOPC Unit incl. Nios® II/f soft processor, GPIO, UART and DDR2 SDRAM control
• Wishbone-to-Avalon®/Avalon®-to-Wishbone bridges
• Reset controller, interrupt controller, SMBus controller, GPIO controller
• M-Module™ to Wishbone bridge, ID EEPROM emulation
• 16Z045_FLASH - Flash interface
• The FPGA offers the possibility to add customized I/O functionality. See FPGA.

USM™ Slot
• One slot populated with bare USM™ module US0
• US0 only passes through signals between the FPGA and the front connector and reduces +5V input levels to 3.3V system I/O level

Connection to evaluation board
• SCSI 2 connector, 50-pin HP D-Sub receptacle
• 46 I/O signals from/to evaluation board, FPGA-controlled

M-Module™ Characteristics
• Compliant with M-Module™ standard
• A08, A24, D08, D16, D32, INTA, IDENT

Accessories

SA1 RS232 SA-Adapter™

SCSI 2 cable

Please note that the kit does not include an M-Module™ carrier board! You should install the M-Module™ on a suitable carrier in a test system of your choice.

Electrical Specifications

Supply voltage/power consumption:
• M199 with US0: +5V (-3%/+5%), 1000mA max.
• AD99: +5V, consumption only depends on SA-Adapter™ used, current drawn on I/O lines and LEDs driven, with 1 SA1 and all 8 LEDs on approx. 100mA typ.
• SA1: +5V (-3%/+5%), 40mA typ.

MTBF:
• M-Module™ USM™ Development Kit (total): 319,364h @ 40°C according to IEC/TR 62380 (RDF 2000)
• M199: 533,355h @ 40°C according to IEC/TR 62380 (RDF 2000)
• US0: 1,989,261h @ 40°C according to IEC/TR 62380 (RDF 2000)
• AD99: 1,469,985h @ 40°C according to IEC/TR 62380 (RDF 2000)
• SA1: 1,870,000h @ 50°C (derived from MIL-HDBK-217F)

Mechanical Specifications

Dimensions:
• M199: conforming to M-Module™ standard
• US0: conforming to USM™ standard
• AD99: standard single Eurocard, 100mm x 160mmm
• SA1: 32mm x 42mm

Weight:
• M199: 70g
• US0: 20g
• AD99: 90g
• SA1: 16g

Environmental Specifications

Temperature range (operation):
• 0..+60°C
• Airflow: min. 10m³/h

Temperature range (storage): -40..+85°C

Relative humidity (operation): max. 95% non-condensing

Relative humidity (storage): max. 95% non-condensing

Altitude: -300m to + 3,000m

Shock: 15g/11ms

Bump: 10g/16ms

Vibration (sinusoidal): 2g/10..150Hz

Conformal coating on request

Safety

PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

EMC

Tested according to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and IEC1000-4-4 (burst)

Software Support

Nios® sample design for Quartus® II development tools

Flash update tools for Windows®, Linux, VxWorks®

Driver software depending on implemented FPGA functions

For more information on supported operating system versions and drivers see Software.

Flexible Configuration

Customized I/O functions can be added to the FPGA.

It depends on the board type, pin counts and number of logic elements which IP cores make sense and/or can be implemented. Please contact MEN for information on feasibility.

You can find more information on our web page "User I/O in FPGA"

FPGA Capabilities

FPGA Altera® Cyclone® II EP2C35
• 33,216 logic elements
• 483,840 total RAM bits

Connection
• Functions can be linked to Wishbone or Avalon® bus
• Available pin count: 46 pins (FPGA to USM™)
• Functions available via USM™ at front I/O connector of M199 and onboard connectors of AD99 evaluation board
• SA-Adapters™ can be used on AD99 to realize the physical lines.

MEN offers an FPGA Development Package as well as Flash update tools for different operating systems.

MEN IP Cores

MEN offers a large number of standard IP cores.

Examples:
• IDE (e.g. PIO mode 0, UDMA mode 5)
• UARTs
• CAN bus
• Display control
• Fast Ethernet (10/100Base-T)
• ...

For IP cores developed by MEN please refer to our IP core overview.
• IP Core compare chart (PDF)

MEN also offers development of new (customized) IP cores.

Third-Party IP Cores

Third-party IP cores can also be used in combination with MEN IP cores.

Examples:
• www.altera.com
• www.opencores.org

FPGA Design Environment

Altera® offers free download of Quartus® II Web Edition
• Complete environment for FPGA and CPLD design
• Includes schematic- and text-based design entry
• Integrated VHDL and Verilog HDL synthesis and support for third-party synthesis software
• SOPC Builder system generation software
• Place-and-route, verification, and programming

Altera® Quartus® II Web Edition FPGA design tool

Article No.	Description	More
FPGA
16M199-00	Nios® M-Module™ USM™ FPGA Development Package (MEN) (without Altera® Quartus® II) (license included in M-Module™ USM™ FPGA Development Kit)	Download Details
Linux
This product is designed to work under Linux. See below for potentially available separate software packages from MEN.
13Z100-91	Linux FPGA update tool (MEN)	Download Details
Windows
This product is designed to work under Windows®. See below for potentially available separate software packages from MEN.
13Z100-70	Windows® FPGA update tool (MEN)	Download Details
VxWorks
This product is designed to work under VxWorks®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z100-60	VxWorks® FPGA update tool (MEN)	Download Details
QNX
This product is designed to work under QNX®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z100-40	QNX® FPGA update tool (MEN)	Download Details

For operating systems not mentioned here contact MEN sales.