CompactPCI Serial Update – Alterations in Revision 2
More Flexibility for System Configuration
Especially in mobile applications with high power dissipation and the demand for a maintenance-free design, conduction cooling systems are an appropriate solution. As these solutions mostly do not support interfaces on the front, revision 2 of CompactPCI Serial now defines additional I/O signals on the P6 connector of the system slot. In total there are now 58 pins available, instead of just 10 pins in revision 1. The choice and combination of the signals is not fixed and therefore freely configurable. To connect several 19’’ systems, PCI Express is now also available on the backplane.
The additional rear I/O pins take advantage of the usage of mezzanine boards for Ethernet signals via the P6 connector, as already described in revision 1. Routing the Ethernet signals directly over the mezzanines and not over the CPU boards has a couple of benefits: depending on the application the number of Ethernet channels can vary by choosing the appropriate mezzanine without the need for different CPU cards. The combination of the desired rear I/O with any number of Ethernet channels offers highest flexibility and does not require any additional carrier board.
The second major improvement is the possibility for placing the system slot also on the right side of the backplane, giving more leeway for the system configuration. Until now the system slot could only be placed at the leftmost slot of the backplane.
In order to make the wording of the specification document clearer and more user-friendly, the coupling of SATA, the I2C system management bus, the maximum size of conduction cooling systems and the wiring of the backplane have been defined more clearly to avoid misinterpretation of the specification.
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