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Jan 30, 2015

Flexible FPGA Chip for Safety-Critical AFDX Applications

The FPGA-Chip CS1 with integrated AFDX protocol offers a flexible alternative for communication in airplanes. Especially designed for the demands of safety-critical avionic applications, the DO-254-compliant FPGA can be certified up to DAL-A (certification support package for DAL-D available in March 2015).

CS1 - FPGA with Integrated AFDX/ARINC-664
  • AFDX functionality integrated in a flash based FPGA
  • SEU (Single Event Upset) resistant
  • On-board AFDX protocol stack implementation
  • Interoperable with Airbus and Boeing (ES-DFS 4.1 and ARINC-664p7)
  • DAL-A/B certifiable
  • Host driver with ARINC-653 compliant port API
  • Integrated SNMP/ICMP support

Nuremberg, Germany - January 26, 2015. The FPGA-Chip CS1 with integrated AFDX protocol offers a flexible alternative for communication in airplanes. Especially designed for the demands of safety-critical avionic applications, the DO-254-compliant FPGA can be certified up to DAL-A (certification support package for DAL-D available in March 2015).

Customizable and independent of form factor

The FPGA chip CS1 offers customers the possibility to build AFDX-based communication systems, for the first time independent of a form factor. The FPGA can be installed directly onto the boards of an AFDX end system. It therefore eliminates the need for an additional module to integrate AFDX protocols.

Also available as a PMC module

For evaluation, the PMC module P522 from MEN can be used - it is also available as COTS products and can be also used as an alternative to the PMCs already existing on the market.

Being an FPGA component, the CS1 allows customization to realize, for example, gateway solutions like AFDX to CAN, AFDX to Standard Ethernet or AFDX to ARINC 429. Developed according to the ARINC 664P7-1 standard, and in consideration of the specific Airbus and Boeing AFDX requirements, the CS1 can be used in applications of both airplane suppliers.

Thanks to the flash based architecture with tripled redundant logic, the FPGA chip is prepared for safety-critical demands and is therefore, for example, SEU-resistant (Single Event Upset) and offers real-time capability.

The host driver with an ARINC-653 compliant port API (Application Programming Interface) prevents the influence of critical and non-critical applications within one complete system. The up to 255 receive VLs (Virtual Link) and 64 transmit VLs ensure a safe and deterministic data transfer through determined band widths.

The integrated SNMP/ICMP protocols support the host CPU with the network management therefore providing more performance on the CPU.

The independency of one airplane supplier or form factor plus the flexible modification for customer's wishes, make the CS1, and the appropriate PMC module P522, a safe choice for critical avionic applications.


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