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Jan 19, 2015

Flexible FPGA Chip with Integrated AFDX Protocol

MEN Micro Inc., a world-renowned provider of embedded computing and I/O solutions for mission-critical industrial, mobile and harsh environment applications, has released the CS1, an FPGA chip with an integrated AFDX protocol that provides a flexible alternative for communication in airplanes. 

CS1 - FPGA with Integrated AFDX/ARINC-664

BLUE BELL, Pa. January 2015 – MEN Micro Inc., a world-renowned provider of embedded computing and I/O solutions for mission-critical industrial, mobile and harsh environment applications, has released the CS1, an FPGA chip with an integrated AFDX protocol that provides a flexible alternative for communication in airplanes.

The customizable CS1 enables users to build AFDX-based communication systems independent of a form factor. The new FPGA can be installed directly on the boards of an AFDX end system. This eliminates the need of an additional module to integrate the AFDX protocols, which send information between avionics subsystems in airborne applications.

Specifically designed for the demands of safety-critical avionic applications, the new chip is a DO-254-compliant FPGA, certifiable up to DAL-A, with DAL-D certification support package available in March 2015.

Developed according to ARINC 664P7-1, and in consideration of the specific Airbus and Boeing AFDX requirements, the CS1 can be used in applications of both airplane suppliers.

Thanks to its flash-based architecture with tripled, redundant logic, the FPGA chip easily meets safety-critical demands, such as being SEU-resistant (Single Event Upset) and offering real-time capability.

The CS1 is also offered in MEN Micro's P522 PMC I/O mezzanine card–available as a COTS product—that can be used as an alternative to PMCs already on the market, or for evaluation purposes.

Being an FPGA component, the CS1 is customizable to enable such functions as gateway solutions including AFDX-to-CAN, AFDX-to-standard Ethernet or AFDX-to-ARINC 429.

The host driver with an ARINC-653 compliant port API (Application Programming Interface) prevents the influence of critical and non-critical applications within one complete system.

The CS1 supports two full duplex AFDX networks based on standard IEEE 802.3 Ethernet and applies protocol stack implementation. With up to 255 receive VLs (Virtual Links) and 64 transmit VLs, the chip ensures safe and deterministic data transfer through determined bandwidths.

The integrated SNMP/ICMP protocols support the host CPU with the network management, enabling higher performance from the CPU.

The ability to meet multiple airplane supplier requirements and form factors, plus the flexibility to modify the chip for specific application requirements, make the CS1 as well as the appropriate PMC module P522, a safe choice for critical avionic applications.

Technical Specifications:

  • AFDX functionality integrated in a flash-based FPGA
  • SEU resistant
  • DO-254-compliant and DAL-A certified, with DAL-D in March 2015
  • Standalone chip or offered on P522 PMC module


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