M199 - FPGA-based USM Main M-Module

M-Module

This product has been discontinued.

The mezzanine card M199 is an USM main M-Module with FPGA functionality.

Functionality

User-defined through FPGA
Line drivers and/or additional hardware implemented on USM Universal Submodule (not included)

Memory

32MB SDRAM memory
- Soldered
- DDR2
- 133MHz memory bus frequency
- FPGA-controlled
8MB non-volatile Flash
- 2MB for FPGA data
- 6MB for user data or Nios firmware
- FPGA-controlled

FPGA

USM Slot

Miscellaneous

Eight onboard LEDs at bottom side of board, FPGA-controlled
- One used to show FPGA load status, seven free for user-defined functions (GPIO)
I²C interface to detect the USM module

M-Module Characteristics

Compliant with M-Module standard
The actual characteristics implemented depend on the USM module and FPGA function!
Prepared for A08, A24, D08, D16, D32, INTA, INTB, INTC, DMA08, DMA16, DMA32, TRIGI, TRIGO, IDENT

Peripheral Connections

Via front panel on a shielded 50-pin HP D-Sub SCSI 2 receptacle connector

Electrical Specifications

Isolation voltage:
- Voltage depends on implementation and signal routing of USM
- Voltage between the connector shield and isolated ground is limited to approx. 180V using a varistor; AC coupling between connector shield and isolated ground through 47nF capacitor
Supply voltage/power consumption:
- +5V (-3%/+5%), 400mA max. (M199 only), 1000mA max. (M199 with USM)
MTBF: 533,355h @ 40°C according to IEC/TR 62380 (RDF 2000)

Mechanical Specifications

Environmental Specifications

Safety

PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

EMC

Tested according to EN 55022 (radio disturbance), IEC 61000-4-2 (ESD) and IEC 61000-4-4 (burst)

Software Support

Nios sample design for Quartus II development tools
Flash update tools for Windows, Linux, VxWorks
Driver software depending on implemented FPGA functions
For more information on supported operating system versions and drivers see Software.

FPGA Capabilities

FPGA Altera Cyclone II EP2C35
- 33,216 logic elements
- 483,840 total RAM bits
- Supports Nios II soft processor
Connection
- Functions can be linked to Wishbone or Avalon bus
- Available pin count: 46 pins (FPGA to USM)
- Functions available via USM at front I/O connector
MEN offers an FPGA Development Package as well as Flash update tools for different operating systems.

I/O

Front Connections

25-pin D-Sub receptacle connector instead of 50-pin SCSI 2 connector
For 25 I/O signals
For the availability and assignment of I/O signals please see the USM Specification

Some of these options may only be available for large volumes.

Please ask our sales staff for more information.