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CS1 - FPGA with Integrated AFDX/ARINC-664

Interface Chip

The CS1 is a FPGA chip with AFDX-protocol which can be adapted to AFDX/CAN, AFDX/Standard Ethernet, AFDX/ARINC 429 gateway solutions.

Download data sheet

  • CS1 Product ImageAFDX®/ARINC-664 P7-1 Interface Chip
  • CS1 Product Image

Main Features

  • AFDX functionality integrated in a Flash based FPGA
  • SEU immune configuration
  • On-board AFDX protocol stack implementation
  • Interoperable with Airbus and Boeing
  • DAL-D certifiable/prepared for DAL-A
  • Host driver with ARINC-653 compliant port API
  • Integrated SNMP/ICMP agent
  • Implemented on the P522 AFDX Interface PMC
CS1 Product Image

Technical Data

AFDX Usage Domain
  • Compatible with Airbus End System Detailed Functional Specification
  • Receive Operation
    • Up to 256 virtual reception links (VL)
    • Up to 32 ports per VL
    • Up to 1024 receive ports in total
  • Transmit Operation
    • Up to 64 virtual transmission links (VL)
    • Up to 32 ports per VL
    • Up to 1024 transmit ports in total
    • BAG between 0.1 ms and 204.7 ms in steps of 0.1 ms
  • Support of AFDX Queueing and Sampling Ports as defined in ARINC664-P7
  • Support of SAP and extended SAP as defined in ARINC664-P7
  • Support of direct communication via IP layer
  • Support of Management Information Base (MIB) for AFDX and SAP communication as defined in ARINC664-P7
Reserved Bridge I/O Domain
Prepared for additional bus interfaces accessible by the host (on request)
AUX Domain
  • SNMP Agent
  • ICMP Agent
  • Completely independent of host communication
Memory Size Support
  • AFDX TX/RX buffer support:
    • Up to 32 MB receive data
    • Up to 32 MB transmit data
    • FPGA-controlled and ECC/CRC protected
  • Up to 128 MBit non-volatile Flash
    • For AFDX configuration data
    • FPGA-controlled and CRC protected
    • Minimum support of 16 AFDX configurations in Flash
External Interfaces
  • 6 General Purpose Digital Inputs usable for:
    • Location indication
    • In flight / on ground indication
  • PCI slave
    • Standard 32-bit/33-MHz
  • MII AFDX Channel A/B
    • 100BASE-TX, 10BASE-T
  • SPI Flash Memory
    • Store AFDX configuration tables
  • 2x RAM Buffer Memory
    • Store AFDX packets
    • Independent debug and test interface for the AUX domain
  • JTAG
    • Access to FPGA for programming, debugging and testing
Configuration Interfaces
  • Software tool for programming AFDX configuration
  • ARM Cortex-M3 (SNMP/ICMP) enable
  • AFDX configuration write protection enable
  • Complete AFDX protocol implementation
  • SEU immune configuration
  • SNMP and ICMP agents
Electrical Specifications
Power consumption:
  • 1.2 V Core Supply - Consumption tbd
  • 2.5 V IO Supply for SRAM Interface - Consumption tbd
  • 3.3 V IO Supply for PCI Interface - Consumption tbd
Environmental Specifications (Dependent on Host Board)
  • Temperature range (operation):
    • -40 to +100°C (qualified components)
  • Temperature range (storage): -55 to +150°C
  • tbd
Software Support
  • Linux
  • For more information on supported operating system versions and drivers see Software.

Ordering Information

Standard CS1 Models

AFDX DAL-D host interface PCI32/33MHz, ARM Cortex-M3 for SNMP/ICMP, -40°C to +100°C

Related Hardware
P522 - AFDX/ARINC-664 Interface PMC

AFDX PMC, DAL-D, 4 MByte RX & 4 MByte TX Memory Buffer, 64 MBit AFDX configuration Flash, -40°C to +85°C with qualified components




Linux native driver (MEN) for CS1 AFDX IP Core