16Z037_GPIO - GPIO Controller with Serial Interface
FPGA IP Core
This functional block is a General Purpose Input/Output core with 8 input/output ports via a serial SPI interface.
- Logic elements (Altera Cyclone device family): 120 typ.
- Pin count: 4
- Wishbone bus interface compliant with Wishbone Specification B.3
- 8-bit data transfer, 66MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
- Up to 8 general purpose input/output ports
- Interrupt on input signal change (rising and/or falling edge)
- Separate programmable interrupts for each input
- Re-readable outputs
- Generics for all register values
MDIS5 System (and Device Driver) Package (MEN) for VxWorks. This software package includes most standard device drivers available from MEN.
MDIS4/2004 system (and device driver) package (MEN) for QNX, source code. This software package includes most standard device drivers available from MEN.
MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO