Log in News & Media | Downloads | Corporate | Careers | Legal Notes
+49 911 99 33 5-0
info@men.de

16Z077_ETH - Ethernet MAC Interface

FPGA IP Core

The 16Z077_ETH is an Ethernet MAC IP core which allows communication between an external physical Ethernet chip and a host application.

Download data sheet

Main Features

  • FPGA IP Core
  • 10Base-T Ethernet support
  • MAC layer functions
16Z077_ETH Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 2200
  • Pin count min.: 18
  • RAM: 6 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles (master)
    • Single read/write
  • Supported Wishbone bus cycles (slave)
    • Single read/write
Ethernet Functionality
  • 10Base-T
  • MAC layer functions
  • Full duplex
  • Internal RAM for 128 TX/RX buffer descriptors

Software

Linux
13Z077-90

Linux native driver (MEN) for 16Z077_ETH and 16Z087_ETH

Documentation