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16Z087_ETH - Ethernet MAC Interface
FPGA IP Core
The 16Z087_ETH is an Ethernet MAC IP core which allows communication between an external physical Ethernet chip and a host application.
Main Features
- FPGA IP Core
- 10/100Base-T Ethernet support
- MAC layer functions
Technical Data
Size
- Logic elements (Altera Cyclone device family): 3400 typ.
- Pin count min.: 14 (without half duplex and error signal)
- Pin count typ.: 18
- RAM: 9 x M4K (Cyclone I and II) or 5 x M9K (Cyclone III)
System-Bus Interface
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, up to 125 MHz bus frequency
- Supported Wishbone bus cycles (master)
- Single read/write
- Burst read/write
- Supported Wishbone bus cycles (slave)
- Single read/write
Ethernet Functionality
- 10Base-T, 100Base-T, 100Base-TX
- MAC layer functions
- Half duplex / full duplex
- Flow control according to IEEE 802.3x
- 64 transmit and 64 receive buffers
Software
Linux 13Z077-90
Linux native driver (MEN) for 16Z077_ETH and 16Z087_ETH
13MD05-90
MDIS5 System (and Device Driver) Package (MEN) for Linux.
This software package includes most standard device drivers available from MEN.
Windows 13Z087-70
Windows native driver (MEN) for 16Z087_ETH (Ethernet controller)
QNX 13Z087-40
QNX native driver (MEN) for 16Z087_ETH
Documentation
Data Sheets
User Manuals
Errata & Technical Information