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19M199- - M-Module USM FPGA Development Kit

This product has been discontinued.

USM Universal Submodules make M-Modules more flexible, cost and time-saving than ever. A main M-Module gets its specific function through the IP cores implemented inside its onboard FPGA.

Download data sheet

  • 19M199- Product ImageConfiguration example: USM M-Module development kit
  • 19M199- Product ImageConfiguration example: USM M-Module development kit equipped with a US0
  • 19M199- Product Image
  • 19M199- Product Image

Main Features

  • 1 Main M-Module M199 for USM Universal Submodules:
  • 1 FPGA 33,216 LE
  • 32 MB DDR2 SDRAM, 8 MB Flash
  • 1 bare USM module US0
  • 1 evaluation board with RS232 debug interface
  • 1 FPGA development package:
  • Main bus interface
  • Memory control
  • Nios softcore
  • Wishbone/Avalon bridges
  • For user-defined I/O
  • 1 SCSI cable
  • -40 to +85 °C with qualified components
19M199- Product Image

Technical Data

Evaluation Board AD99
  • 50-pin connection to M199
    • SCSI 2 connector
    • 46 I/O signals from/to M199
  • Six SA-Adapter slots
    • For direct onboard connection
    • 46 I/O signals from/to SCSI 2 connector
    • RS232 SA-Adapter SA1 included
  • Three 20-pin I/O connectors
    • 46 I/O signals from/to SCSI 2 connector
  • Eight user LEDs at front, driven by I/O signals
M-Module M199 (USM main module)
  • CPU
    • Nios II soft processor
    • 66MHz
  • Memory
    • 32MB DDR2 SDRAM, soldered
    • 8MB non-volatile Flash, for FPGA data and Nios firmware
  • I/O at front panel (SCSI 2 connector)
    • One LVTTL UART (for RS232 on AD99 via SA1 SA-Adapter)
  • Functions in FPGA
    • Main bus interface
    • Altera SOPC Unit incl. Nios II/f soft processor, GPIO, UART and DDR2 SDRAM control
    • Wishbone-to-Avalon/Avalon-to-Wishbone bridges
    • Reset controller, interrupt controller, SMBus controller, GPIO controller
    • M-Module to Wishbone bridge, ID EEPROM emulation
    • 16Z045_FLASH - Flash interface
    • The FPGA offers the possibility to add customized I/O functionality. See FPGA.
  • USM Slot
    • One slot populated with bare USM module US0
    • US0 only passes through signals between the FPGA and the front connector and reduces +5V input levels to 3.3V system I/O level
  • Connection to evaluation board
    • SCSI 2 connector, 50-pin HP D-Sub receptacle
    • 46 I/O signals from/to evaluation board, FPGA-controlled
  • M-Module Characteristics
    • Compliant with M-Module standard
    • A08, A24, D08, D16, D32, INTA, IDENT
  • SA1 RS232 SA-Adapter
  • SCSI 2 cable
  • Please note that the kit does not include an M-Module carrier board! You should install the M-Module on a suitable carrier in a test system of your choice.
Electrical Specifications
  • Supply voltage/power consumption:
    • M199 with US0: +5V (-3%/+5%), 1000mA max.
    • AD99: +5V, consumption only depends on SA-Adapter used, current drawn on I/O lines and LEDs driven, with 1 SA1 and all 8 LEDs on approx. 100mA typ.
    • SA1: +5V (-3%/+5%), 40mA typ.
  • MTBF:
    • M-Module USM Development Kit (total): 319,364h @ 40°C according to IEC/TR 62380 (RDF 2000)
    • M199: 533,355h @ 40°C according to IEC/TR 62380 (RDF 2000)
    • US0: 1,989,261h @ 40°C according to IEC/TR 62380 (RDF 2000)
    • AD99: 1,469,985h @ 40°C according to IEC/TR 62380 (RDF 2000)
    • SA1: 1,870,000h @ 50°C (derived from MIL-HDBK-217F)
Mechanical Specifications
  • Dimensions:
    • M199: conforming to M-Module standard
    • US0: conforming to USM standard
    • AD99: standard single Eurocard, 100mm x 160mmm
    • SA1: 32mm x 42mm
  • Weight:
    • M199: 70g
    • US0: 20g
    • AD99: 90g
    • SA1: 16g
Environmental Specifications
  • Temperature range (operation):
    • 0..+60°C
    • Airflow: min. 10m³/h
  • Temperature range (storage): -40..+85°C
  • Relative humidity (operation): max. 95% non-condensing
  • Relative humidity (storage): max. 95% non-condensing
  • Altitude: -300m to + 3,000m
  • Shock: 15g/11ms
  • Bump: 10g/16ms
  • Vibration (sinusoidal): 2g/10..150Hz
PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers
Tested according to EN 55022 (radio disturbance), IEC 61000-4-2 (ESD) and IEC 61000-4-4 (burst)
Software Support
  • Nios sample design for Quartus II development tools
  • Flash update tools for Windows, Linux, VxWorks
  • Driver software depending on implemented FPGA functions
  • For more information on supported operating system versions and drivers see Software.


FPGA Capabilities
  • FPGA Altera Cyclone II EP2C35
    • 33,216 logic elements
    • 483,840 total RAM bits
  • Connection
    • Functions can be linked to Wishbone or Avalon bus
    • Available pin count: 46 pins (FPGA to USM)
    • Functions available via USM at front I/O connector of M199 and onboard connectors of AD99 evaluation board
    • SA-Adapters can be used on AD99 to realize the physical lines.
  • MEN offers an FPGA Development Package as well as Flash update tools for different operating systems.

Ordering Information

SA15 - 8-Channel Binary I/O Adapter

8 digital I/O channels, -40..+85°C qualified, no RoHS

SA8 - CAN Bus ISO High-Speed Interface Adapter

CAN bus ISO high-speed, optically isolated, 0..+60°C

SA3 - RS232 Interface Adapter

RS232, optically isolated, 0°C to +60°C

SA2 - RS422/RS485 Interface Adapter

RS422/485, full duplex, optically isolated, 0°C to +60°C

SA2 - RS422/RS485 Interface Adapter

RS422/485, half duplex, optically isolated, 0°C to +60°C


If you have implemented the corresponding IP core in the FPGA, you may be able to use the following SA-Adapters as a physical layer on your USM evaluation kit:

SA1 - RS232 Interface Adapter

RS232, not optically isolated, 0°C to +60°C




Linux FPGA update tool (MEN)


Windows FPGA update tool (MEN)


VxWorks FPGA update tool (MEN)


QNX FPGA update tool (MEN)


Nios M-Module USM FPGA Development Package (MEN) (without Altera Quartus II) (license included in M-Module USM FPGA Development Kit)

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