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16Z034_GPIO - GPIO Controller

FPGA IP Core

The GPIO controller is a General Purpose Input/Output module with 8 input/output ports.

Download data sheet

Main Features

  • FPGA IP Core
  • 8 input/output ports
  • Separate programmable interrupts for each input
  • 8-bit debouncer logic for input signals
  • Outputs configurable as open drain or regular digital ports
  • Wishbone bus interface
16Z034_GPIO Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): max. 250 (depending on usage of debouncer inputs)
  • Pin count min: 1
  • Pin count max: 8
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 8-bit data transfer, 66MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
GPIO Functionality
  • Up to 8 general purpose input/output ports
  • Optional debouncer for inputs
  • Optional open drain functionality
  • Interrupt on input signal change (rising and/or falling edge)
  • Re-readable outputs
  • Generics for all register values
Software Support
  • MEN Driver Interface System (MDIS for Windows, Linux, VxWorks, QNX, OS-9)
  • For more information on supported operating system versions and drivers see Software.

Software

Windows
13Z017-70

MDIS4/2004 / MDIS5 Windows driver (MEN) for 16Z034_GPIO devices

VxWorks
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO

QNX
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO

OS-9
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO