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16Z044_DISP - Display Controller

FPGA IP Core

The 16Z044_DISP is a display controller IP core which adds display capabilities to the digital system.

Download data sheet

Main Features

  • FPGA IP Core
  • For VGA, DVI or FPD Link control
  • Resolution up to 1280 x 1024
  • Wishbone bus interface
16Z044_DISP Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 800 typ.
  • Pin count min: 20
  • Pin count max: 48
  • RAM: 6 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33/66/133MHz bus frequency (Master)
  • Supported Wishbone bus cycles (Master)
    • Single read/write
    • Block read
  • 32-bit data transfer, 33/66MHz bus frequency (Slave)
  • Supported Wishbone bus cycles (Slave)
    • Single read/write
Functionality
  • Resolution up to 1280x1024
  • Frequency 60 or 75 Hz
  • Digital VGA
    • Timing relating to the selected graphical resolution
    • 8-bit data for each of the RGB colors (sourced by 5-6-5 RGB data)
    • HSYNC and VSYNC control signals
  • Interface for a VGA-to-DVI chip
    • Clock output as reference for the data
    • Data qualifier output
  • LVDS
    • Up to 2 FPD link ports (based on LVDS)
    • Each FPD link port with 4 differential data pairs and 1 differential clock pair
    • FPD link interface supports various display panels

Software

Linux
13MD05-90

MDIS5 System (and Device Driver) Package (MEN) for Linux. This software package includes most standard device drivers available from MEN.

Windows
13Z044-70

Windows native driver (MEN) for 16Z044_DISP (frame buffer)

VxWorks
13Z044-60

VxWorks driver (MEN) for 16Z044_DISP (frame buffer)

QNX
13Z044-40

QNX native driver (MEN) for 16Z044_DISP (frame buffer)