Log in News & Media | Downloads | Corporate | Careers | Legal Notes
+49 911 99 33 5-0
info@men.de

16Z072_OWB - One-Wire Bus Controller

FPGA IP Core

The 16Z072_OWB is an OWB controller providing a Wishbone interface to access a one wire bus EPROM.

Download data sheet

Main Features

  • FPGA IP Core
  • One wire bus EPROM access
  • Wishbone bus interface
16Z072_OWB Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 700 typ.
  • Pin count min.: 1
  • Pin count max.: 2
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 8-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
Functionality
  • One wire bus data line
  • Programming voltage control line
  • Interrupt line
  • Asynchronous reset
  • Write-, read-, command- and status register to control the EPROM access
  • Asynchronous reset

Documentation