16Z001_SMB - I2C SMBus Controller
FPGA IP Core
The SMBus controller is a bridge between an SMBus and a Wishbone interface. The SMBus features master capabilities, while the Wishbone interface features slave capability.
- Logic elements (Altera Cyclone device family): 550 typ.
- Pin count: 2
- RAM: 1 x 4096 bits
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
- Master operation (revisions 7 and later with Multi-Master support, latest software drivers required!)
- Quick send byte
- Quick receive byte
- Write byte/write word
- Read byte/read word
- Block read/block write
- Read/write I²C message
- Baud rate generator
Linux host driver (MEN) for 16Z001_SMB (I2C)
MDIS5 System (and Device Driver) Package (MEN) for Linux.
This software package includes most standard device drivers available from MEN.