Log in/Register News & Media | Downloads | Corporate | Careers | Contact Request
+49 911 99 33 5-0
info@men.de

16Z001_SMB - I2C SMBus Controller

FPGA IP Core

The SMBus controller is a bridge between an SMBus and a Wishbone interface. The SMBus features master capabilities, while the Wishbone interface features slave capability.

Download data sheet

Main Features

  • FPGA IP Core
  • SMBus master interface
  • Wishbone slave interface
16Z001_SMB Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 550 typ.
  • Pin count: 2
  • RAM: 1 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
SMBus Functionality
  • Master operation (revisions 7 and later with Multi-Master support, latest software drivers required!)
  • Quick send byte
  • Quick receive byte
  • Write byte/write word
  • Read byte/read word
  • Block read/block write
  • Read/write I²C message
  • Baud rate generator
  • Interrupt

Ordering Information

Contact Request! Use this form to get the fastest possible reply.
Please make sure to fill out the complete form, so we can provide quick and specific support.
Your request will be sent to our sales team.

Your information will not be shared!

* required fields

Your Request

Your Contact Data

Please type in the letters and/or numbers that you see in the image on the left (case-sensitive).