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16Z024_SRAM - SRAM Controller

FPGA IP Core

The SRAM controller handles access to static RAMs up to a size of 4 MB. The SRAM address space has a size of 4MB, so a dedicated Base Address Register is used for the SRAM memory space.

Download data sheet

Main Features

  • FPGA IP Core
  • 4 MB SRAM controller
  • Wishbone bus interface
16Z024_SRAM Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 280 typ. (101 typ. for 16Z024-02)
  • Pin count min: 26
  • Pin count max: 60
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency (up to 133 MHz for 16Z024-02)
  • Supported Wishbone bus cycles
    • Single read/write
Functionality
  • Access to memory devices (SRAM, Flash ROM)
  • 16z024
    • Up to 4 MB SRAM
  • 16z024-02
    • 8-bit/16-bit or 32-bit data width
    • Variable memory configuration

Ordering Information

Software

Linux
13MD05-90

MDIS5 System (and Device Driver) Package (MEN) for Linux. This software package includes most standard device drivers available from MEN.

Windows
13Z024-70

MDIS4/2004 / MDIS5 Windows driver (MEN) for 16Z024_SRAM

VxWorks
13Z024-06

MDIS4/2004 / MDIS5 low-level driver sources (MEN) for 16Z024_SRAM

QNX
13Z024-06

MDIS4/2004 / MDIS5 low-level driver sources (MEN) for 16Z024_SRAM

OS-9
13Z024-06

MDIS4/2004 / MDIS5 low-level driver sources (MEN) for 16Z024_SRAM