16Z045_FLASH - Flash Interface
FPGA IP Core
The Flash Interface 16Z045_FLASH is used to connect standard Flash devices to the Wishbone bus via read-only and read/write addressing. The Flash memory can be used to store FPGA configuration images or software applications.
- Logic elements (Altera Cyclone device family): 80 typ.
- Pin count min: 32
- Pin count max: 73
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33/66MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
- Flash interface
- Standard Flash interface timing
- Up to 29 address bits
- 8 or 16 data bits (32 bits possible, but not yet tested in hardware)
- 16 MB memory size support