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16Z058_SRAM - SRAM over SPI Interface

FPGA IP Core

The SRAM over SPI Interface is a normal indirectly addressable memory interface on the Wishbone bus side and connects to the SRAM via an SPI interface.

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Main Features

  • FPGA IP Core
  • SRAM accessed via SPI
  • Wishbone bus interface
16Z058_SRAM Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 245 typ.
  • Pin count: 4
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
  • Indirect addressing
Functionality
  • SRAM over SPI interface
  • Clock reads and writes
  • Automatic address incrementation on multiple read or write cycles

Ordering Information

Documentation