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16Z087_ETH - Ethernet MAC Interface


The 16Z087_ETH is an Ethernet MAC IP core which allows communication between an external physical Ethernet chip and a host application.

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Main Features

  • FPGA IP Core<br />10/100Base-T Ethernet support<br />MAC layer functions
16Z087_ETH Product Image

Technical Data

  • Logic elements (Altera Cyclone device family): 3400 typ.
  • Pin count min.: 14 (without half duplex and error signal)
  • Pin count typ.: 18
  • RAM: 9 x M4K (Cyclone I and II) or 5 x M9K (Cyclone III)
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, up to 125 MHz bus frequency
  • Supported Wishbone bus cycles (master)
    • Single read/write
    • Burst read/write
  • Supported Wishbone bus cycles (slave)
    • Single read/write
Ethernet Functionality
  • 10Base-T, 100Base-T, 100Base-TX
  • MAC layer functions
  • Half duplex / full duplex
  • Flow control according to IEEE 802.3x
  • 64 transmit and 64 receive buffers


Data Sheets
Errata & Technical Information
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