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16Z126_SERFLASH - Serial Flash Interface

FPGA IP Core

The 16Z126_SERFLASH serial Flash interface is used to connect serial Flash devices to the Wishbone bus via read-only and read/write addressing. The Flash memory can be used to store FPGA configuration images or software applications.

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Main Features

  • FPGA IP Core
  • Controls serial Flash devices
  • Wishbone bus interface
16Z126_SERFLASH Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone III device family): 630 typ.
  • Pin count: 4
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33/66MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
Functionality
  • Flash interface
  • Standard Flash interface timing
  • Up to 24 address bits
  • 32 data bits
  • 16 MB memory size support

Ordering Information

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