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13Z087-70 - Windows native driver (MEN) for 16Z087_ETH
Windows native driver (MEN) for 16Z087_ETH
Download 13Z087-70.zip (2010-08-03) ===== [ History of fileset ART/13Z087-70/13Z087-70 ] =====
-----[ Revision 1.11 ]-----
[ 2010-09-03 15:33:14 by CKauntz ]
R:1. IP Core version byte now also contains the interrupt behaviour bit
Window driver always uses the new interrupt behaviour, set this bit
2. Send packets not consequent protected by SendPacketLock
3. Driver package can be used with installsets
4. HardwareID not consistent
M:1. Added support for the interrupt behaviour bit
2. Added SendPacketLock
3. Support for installsets added
4. Fixed Hardware IDs in installation file
-----[ Revision 1.10 ]-----
[ 2010-03-22 17:32:48 by CKauntz ]
R:1. Send packets with different IRQL changes packet order and may lead to
BSOD at NdisMSendComplete
2. Routines declared as pageable but shall not be paged out
3 NdisMAllocateMapRegister creates map registers that were not used
4. Shared memory allocation for each send bufferdescriptor
5. Instance information added to debug message
6. Eventlog information included
7. Miscellaneous information buffer unused
8. Size for each send or receive buffer set to 4k byte
9. Send and receive routines protected by spinlocks
10. ISR may interrupt the DPC and change the IntStatus, information may
get lost while changing IntStatus
M:1.a) Added additional SendPacketLock for MPSendPacket
b) Added eventlog message when skipping completion
2. Removed pagable declaration for that routines
3. Replaced NdisMAllocateMapRegister with NdisMInitializeScatterGatherDma
4. Changed memory organisation for send buffers from one huge buffer
to shared memory allocation for each bufferdescriptor's buffer
5. Added define for debug message instance information
6. Added routines to write information at the event logger
7. Removed miscellaneous buffer and handling
8. Changed size for buffers to be page and cache-line aligned
9. Fixed SpinLock handling at send and receive routines
10.a) Moved IntStatus handling to ISR
b) Splitted IntStatus to SendInterrupt and RecvInterrupt
-----[ Revision 1.9 ]-----
[ 2010-01-28 15:56:24 by CKauntz ]
R:1. Hardware register access by structure may lead to invalid data
2. Hanging system when cable is detached and attached again
3. No PHY register observation
M:1. Changed to use read/write functions for hardware register access
2. Fixed reading modreg register before check for idle bits
3. Added debugsprints for PHY registers in autoneg mode
-----[ Revision 1.8 ]-----
[ 2010-01-22 10:41:22 by CKauntz ]
R:1. Global MP_DebugLevel shared between the instances
2. SpinLock handling incorrect, SpinLock not acquired but released
3. Status NDIS_STATUS_FAILURE at NdisMSendComplete generates an BSOD 0xD1
M:1. Changed DebugLevel configuration to be instance controlled
Configuration can be set by a registry entry
2. Fixed acquire SpinLock
3. Changed Status to NDIS_STATUS_SUCCESS if adapter is not ready
-----[ Revision 1.7 ]-----
[ 2009-12-18 14:33:31 by CKauntz ]
R:1. New configuration for 64 bit driver with NDIS5.x
2. SendWaitList is filled and the sended frames are completed but
LastTxNbrs are free and no further packet will be send directly, so
send next packet from the queue
3. Routines will be preemted by other NDIS routines and change TCB ocject
parameters
4. NIC driver will run under XP and later OS
M:1. Added 64 Bit configurations
2. Added check for packets in SendWaitList and send next packet
3.a) Critical sections sourrouned by send spinlock
b) Moved spinlock protection from within NICFreeSendTCB to the call of
this routine
4. XP driver is based on NDIS 5.x but later OS version are backward
compatible to NDIS 3.0 - 5.x
-----[ Revision 1.6 ]-----
[ 2009-12-14 14:58:35 by CKauntz ]
R:1.a) VNC connection closed after a few seconds
b) High cpu load
c) Two devices do not work reliable
M:1. Restructured driver from 2 layerd driver with upper edge filter driver
to one NIC driver
-----[ Revision 1.5 ]-----
[ 2009-11-20 16:10:43 by CKauntz ]
R: Driver leads to high cpu load, when booted with much traffic
M: Fixed bootup behaviour
-----[ Revision 1.4 ]-----
[ 2009-09-25 16:55:40 by CKauntz ]
R:1. Unknown handling of nested interrupts
2. Frame control interrupts not supported
3. PREFASTVIEW warnings
4. MM1 wrong LED activities
5. P511 does not support current FPGA version and EEPROM access
6. DebugLevel not changeable at runtime below INFORMATION
M:1. Changed masking/unmasking of all interrupts
2. Added debugmessage for unsupported control frame interrupts
3. Added NULL pointer error cases
4. Changed LED settings for the MM1 PHY
5.a) Changed order to generate P511 MAC
b) Added useage of MAC from reg
c) No error for P511 due to unsupported FPGA version
6. Always show debug levels til WARNING
-----[ Revision 1.3 ]-----
[ 2009-08-31 16:39:19 by CKauntz ]
R:1. EEPROM access incomlete
2. Debug information uninteresting in level INFO
3. Hang after a few cycles
M:1. Fixed access to EEPOM
2. Changed level INFO to TRACE or VERBOSE for routine tracing
3. Fixed packet acknoledgement
-----[ Revision 1.2 ]-----
[ 2009-07-31 19:17:57 by CKauntz ]
R:1 2-Way Interface from ndisedge z87 driver
2.New FPGA design with own EEPROM access
3.Stability for UDP and TPC Packets
M:1.Added Interface for faster receive communication
2.EEPROM routines added to access Z87 EEPROM
3.Added direct write and faster call routines
-----[ Revision 1.1 ]-----
[ 2009-05-29 16:49:03 by CKauntz ]
Initial Revision
Licensing Information
-----[ Revision 1.11 ]-----
[ 2010-09-03 15:33:14 by CKauntz ]
R:1. IP Core version byte now also contains the interrupt behaviour bit
Window driver always uses the new interrupt behaviour, set this bit
2. Send packets not consequent protected by SendPacketLock
3. Driver package can be used with installsets
4. HardwareID not consistent
M:1. Added support for the interrupt behaviour bit
2. Added SendPacketLock
3. Support for installsets added
4. Fixed Hardware IDs in installation file
-----[ Revision 1.10 ]-----
[ 2010-03-22 17:32:48 by CKauntz ]
R:1. Send packets with different IRQL changes packet order and may lead to
BSOD at NdisMSendComplete
2. Routines declared as pageable but shall not be paged out
3 NdisMAllocateMapRegister creates map registers that were not used
4. Shared memory allocation for each send bufferdescriptor
5. Instance information added to debug message
6. Eventlog information included
7. Miscellaneous information buffer unused
8. Size for each send or receive buffer set to 4k byte
9. Send and receive routines protected by spinlocks
10. ISR may interrupt the DPC and change the IntStatus, information may
get lost while changing IntStatus
M:1.a) Added additional SendPacketLock for MPSendPacket
b) Added eventlog message when skipping completion
2. Removed pagable declaration for that routines
3. Replaced NdisMAllocateMapRegister with NdisMInitializeScatterGatherDma
4. Changed memory organisation for send buffers from one huge buffer
to shared memory allocation for each bufferdescriptor's buffer
5. Added define for debug message instance information
6. Added routines to write information at the event logger
7. Removed miscellaneous buffer and handling
8. Changed size for buffers to be page and cache-line aligned
9. Fixed SpinLock handling at send and receive routines
10.a) Moved IntStatus handling to ISR
b) Splitted IntStatus to SendInterrupt and RecvInterrupt
-----[ Revision 1.9 ]-----
[ 2010-01-28 15:56:24 by CKauntz ]
R:1. Hardware register access by structure may lead to invalid data
2. Hanging system when cable is detached and attached again
3. No PHY register observation
M:1. Changed to use read/write functions for hardware register access
2. Fixed reading modreg register before check for idle bits
3. Added debugsprints for PHY registers in autoneg mode
-----[ Revision 1.8 ]-----
[ 2010-01-22 10:41:22 by CKauntz ]
R:1. Global MP_DebugLevel shared between the instances
2. SpinLock handling incorrect, SpinLock not acquired but released
3. Status NDIS_STATUS_FAILURE at NdisMSendComplete generates an BSOD 0xD1
M:1. Changed DebugLevel configuration to be instance controlled
Configuration can be set by a registry entry
2. Fixed acquire SpinLock
3. Changed Status to NDIS_STATUS_SUCCESS if adapter is not ready
-----[ Revision 1.7 ]-----
[ 2009-12-18 14:33:31 by CKauntz ]
R:1. New configuration for 64 bit driver with NDIS5.x
2. SendWaitList is filled and the sended frames are completed but
LastTxNbrs are free and no further packet will be send directly, so
send next packet from the queue
3. Routines will be preemted by other NDIS routines and change TCB ocject
parameters
4. NIC driver will run under XP and later OS
M:1. Added 64 Bit configurations
2. Added check for packets in SendWaitList and send next packet
3.a) Critical sections sourrouned by send spinlock
b) Moved spinlock protection from within NICFreeSendTCB to the call of
this routine
4. XP driver is based on NDIS 5.x but later OS version are backward
compatible to NDIS 3.0 - 5.x
-----[ Revision 1.6 ]-----
[ 2009-12-14 14:58:35 by CKauntz ]
R:1.a) VNC connection closed after a few seconds
b) High cpu load
c) Two devices do not work reliable
M:1. Restructured driver from 2 layerd driver with upper edge filter driver
to one NIC driver
-----[ Revision 1.5 ]-----
[ 2009-11-20 16:10:43 by CKauntz ]
R: Driver leads to high cpu load, when booted with much traffic
M: Fixed bootup behaviour
-----[ Revision 1.4 ]-----
[ 2009-09-25 16:55:40 by CKauntz ]
R:1. Unknown handling of nested interrupts
2. Frame control interrupts not supported
3. PREFASTVIEW warnings
4. MM1 wrong LED activities
5. P511 does not support current FPGA version and EEPROM access
6. DebugLevel not changeable at runtime below INFORMATION
M:1. Changed masking/unmasking of all interrupts
2. Added debugmessage for unsupported control frame interrupts
3. Added NULL pointer error cases
4. Changed LED settings for the MM1 PHY
5.a) Changed order to generate P511 MAC
b) Added useage of MAC from reg
c) No error for P511 due to unsupported FPGA version
6. Always show debug levels til WARNING
-----[ Revision 1.3 ]-----
[ 2009-08-31 16:39:19 by CKauntz ]
R:1. EEPROM access incomlete
2. Debug information uninteresting in level INFO
3. Hang after a few cycles
M:1. Fixed access to EEPOM
2. Changed level INFO to TRACE or VERBOSE for routine tracing
3. Fixed packet acknoledgement
-----[ Revision 1.2 ]-----
[ 2009-07-31 19:17:57 by CKauntz ]
R:1 2-Way Interface from ndisedge z87 driver
2.New FPGA design with own EEPROM access
3.Stability for UDP and TPC Packets
M:1.Added Interface for faster receive communication
2.EEPROM routines added to access Z87 EEPROM
3.Added direct write and faster call routines
-----[ Revision 1.1 ]-----
[ 2009-05-29 16:49:03 by CKauntz ]
Initial Revision
Licensing Information
Supported Operating System
Windows XP
Supported MEN Boards
- MM1
- RC1
- P511
- F11S
Included Documentation
Readme file in ZIP archive
Licensing Information
This article is free of charge.
Ordering Information & Downloads
Main Software
13Z087-70
Windows native driver (MEN) for 16Z087_ETH (Ethernet controller)